Next-generation superconducting qubits via defect and phonon engineering
Abstract: Fault-tolerant quantum computation requires further advances in lowering physical qubit error rates in scalable architectures. In this talk, I will present our work on superconducting quantum devices to reduce error rates and resource overheads in processors. I will discuss how defects and interfaces in silicon limit superconducting qubit performance. I will present our discovery of interface piezoelectricity at a superconductor-silicon junction and the impact of this effect on superconducting qubits.



